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GW3887A preliminary data sheet conexant systems, inc. do-406971-ds november 12, 2004 proprietary - use pursuant to nda issue 2 wireless lan integrated medium access controller with baseband processor the conexant GW3887A wireless lan integrated media access controller with baseband processor is part of both the prism gt? single band and prism wwr? dual band radio chip sets. the GW3887A directly interfaces with conexant?s isl3686b single band direct conversion transceiver. adding conexant?s isl3084 5ghz vc o and isl3980 power amp completes an end-to-end wlan chip set solution compliant with 802.11b/g standards. additionally, the GW3887A directly inte rfaces with conexant?s isl3692 dual band direct conversion transceiver. adding conexant?s isl3092 11ghz vco and isl3992 dual band power amp completes an end-to-end wlan chip set solution compliant with 80 2.11a/b/g/h/i/ j standards. the 802.11 protocol is implemented in firmware supporting custom wlan solutions. the GW3887A improvements over the gw3887 include the addition of an internal 48mhz oscillator, which eliminates several external components from the radio design. software implements the full ieee 802.11 wireless lan mac protocol. it supports bss and ibss operation under dcf, and operation under the optional point coordination function (pcf). active scanning is performed autonomously once initiated by host command. host interface command and status handshakes allow concurrent operations from multi-threaded i/ o drivers. orthogonal frequency division multiplexing (ofdm) of 52 sub-carriers modulated with bpsk, qpsk, 16qam or 64qam and a variety of convolutional coding rates provides 8 selectable data rates at 2.4ghz and 5ghz. differential phase shift keying modulation schemes, dbpsk and dqpsk with data scrambling capability along with complementary code keying provide an additional 4 selectable data rates at 2.4ghz. built-in flexibility allows the GW3887A to be configured for a range of applications. the mac is based on the arm 946e processor core that offers a wide variety of code development support tools. the GW3887A is housed in a thin plastic bga package suitable for usb 2.0 wireless lan small form factor circuit card applications. features ? firmware implements the full ieee 802.11a/b/g/h/i/j wireless lan mac protocols ? internal wep engine allows 64 or 128 bit encryption ? aes hardware accelerator ? start-up modes allow the usb vendor and device id to be initialized from a small external serial eeprom. this allows firmware to be downloaded from the host. ? on-chip sram memory ? a low frequency cr ystal oscillator can maintain time, which allows the high frequency clock source to be powered off during sleep mode. ? firmware controlled antenna diversity ? data rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, & 54mbps ? modulation: ofdm with bpsk, qpsk, 16qam, 64qam; dbpsk; dqpsk and cck ? convolutional coding and interleaving on all ofdm rates ? targeted for ofdm multipath delay spreads >800ns for 6mbps, and >100ns for 54mbps ? targeted for cck multipath delay spreads >90ns at 11mbps, >200ns at 5.5mbps and >360ns at 1 and 2mbps ? direct interface with the isl3692 and isl3686 direct conversion transceiver ? usb 2.0 wireless lan adapters figure 1: simplified block diagram mac bb processor a/d d/a GW3887A sram usb 2.0 interface
GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 2 proprietary - use pursuant to nda issue 2 1 signal descriptions table 1 provides detailed pin information. table 1: GW3887A signal descriptions (sheet 1 of 5) pin name bga ball assignment pad type pin i/o type description corevddd a1 supply none digital core supply(1.8v) corevddd a10 supply none digital core supply(1.8v) iovddd a11 supply none digital io supply (3.3v) gndd a12 supply none digital io and core ground corevddd a13 supply none digital core supply(1.8v) iovddd a14 supply none digital io supply (3.3v) test1 a15 bidir as output none bbp testbus test6 a16 bidir as output none bbp testbus serclk a2 input serial host clock serdin a3 bidir serial host data in for 4-wire interface. bidir for 3 wire interface corevddd a4 supply none digital core supply(1.8v) iovddd a5 supply none digital io supply (3.3v) tdi a6 bidir as input up jtag test serial data input corevddd a7 supply none digital core supply(1.8v) iovddd a8 supply none digital io supply (3.3v) tmsel2 a9 bidir as input down testmode select pin gp2-13 b1 bidir up general purpose utmi-2 b10 input none utmi_linestate[1] utmi-1 b11 input none utmi_linestate[0] test4 b12 bidir as output none bbp testbus gndd b13 supply none digital io and core ground tstclk44in b14 schmitt input down ate 44mhz clock in tstclk80in b15 schmitt input down ate 80mhz clock in corevddd b16 supply none digital core supply(1.8v) iovddd b2 supply none digital io supply (3.3v) gndd b3 supply none digital io and core ground uartsin b4 schmitt input down uart serial data input gndd b5 supply none digital io and core ground tms b6 bidir as input up jtag test mode select tdo b7 bidir none jtag test serial data output tmsel1 b8 bidir as input down testmode select pin corevddd b9 supply none digital core supply(1.8v) gp2-11 c1 bidir up cstschg test10 c10 bidir as output none bbp testbus test9 c11 bidir as output none bbp testbus test3 c12 bidir as output none bbp testbus test2 c13 bidir as output none bbp testbus test0 c14 bidir as output none bbp testbus (lsb) iovddd c15 supply none digital io supply (3.3v) clkout c16 bidir as output none 40mhz clock out uartsout c2 bidir as output none uart output pad sercs_n c3 input serial host chip select serint c4 output serial host interrupt
november 12, 2004 GW3887A data sheet do-406971-ds conexant systems, inc. issue 2 proprietary - use pursuant to nda 3 resetn c5 schmitt input up active low reset for chip gndd c6 supply none digital io and core ground tmsel3 c7 bidir as input down testmode select pin tmsel0 c8 bidir as input down testmode select pin gndd c9 supply none digital io and core ground iovddd d1 supply none digital io supply (3.3v) test7 d10 bidir as output none bbp testbus test5 d11 bidir as output none bbp testbus corevddd d12 supply none digital core supply(1.8v) utmi-0 d13 input none utmi_clk oscenable d14 bidir as output none canned oscillator enable signal, high is active gndd d15 supply none digital io and core ground corevddd d16 supply none digital core supply(1.8v) gp2-12 d2 bidir up multi-ice rtck gp2-9 d3 bidir up led1 activity led (and uart baudout_n) serdout d4 output none serial host data out for 4-wire interface utmi-3 d5 output none utmi_txvalid trstn d6 bidir as input up jtag test reset tck d7 bidir as input up jtag test clock test11 d8 bidir as output none bbp testbus (msb) test8 d9 bidir as output none bbp testbus corevddd e1 supply none digital core supply(1.8v) gndd e13 supply none digital io and core ground iovddd e14 supply none digital io supply (3.3v) lna_h/l e15 bidir as output none agc 30db pad signal clkin40 e16 schmitt input none high frequency (40mhz) crystal pad cell gp1-3 e2 bidir down pa_pe5g 5ghz pa enable gp1-2 e3 bidir down usb_vbus faa_hrdn e4 schmitt up hardware input for faa switch iovddd f1 supply none digital io supply (3.3v) analog_test f13 input/output - voltage used in conjuction with ate testing vssa33c f14 supply - usb2.0 common analog ground vssdphy f15 supply none gnd for digital portion of usb phy vdddphy f16 supply none 1.8v supply for digital portion of usb phy gp2-4 f2 bidir down uart dtr_n gp2-7 f3 bidir down uart cts_n gp1-15 f4 bidir up faamode_n corevddd g1 supply none digital core supply(1.8v) nc g13 none none no connect, no pad vdda33c g14 supply - usb2.0 common analog supply xi g15 analog - 48-mhz crystal or cloc k input if external clock used xo g16 analog - 48-mhz crystal output. unused unless using external crystal gp2-6 g2 bidir down uart rts_n gp2-8 g3 bidir up uart dcd_n gndd g4 supply none digital io and core ground gp2-2 h1 bidir down faa led (led2) table 1: GW3887A signal descriptions (sheet 2 of 5) pin name bga ball assignment pad type pin i/o type description
GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 4 proprietary - use pursuant to nda issue 2 nc h13 none none no connect, no pad vssa33t h14 supply - usb2.0 transceiver ground rext h15 input - external resistor 3.01k ohm (1%) vdda33t h16 supply - usb2.0 transceiver supply gp1-13 h2 bidir up radio_pe gndd h3 supply none digital io and core ground gp2-5 h4 bidir down uart dsr_n iovddd j1 supply none digital io supply (3.3v) vssa33t j13 supply - usb2.0 transceiver ground nc j14 none none no connect, no pad vssa33t j15 supply - usb2.0 transceiver ground dm j16 analog - usb2.0 data m signal corevddd j2 supply none digital core supply(1.8v) gp2-1 j3 bidir float serial flash data (serdat) gp2-3 j4 bidir down general purpose gp1-14 k1 bidir up antsel comppabias k13 analog none compensation cap for pa bias dac pabias5g k14 analog none pabiassel5g = 1 for bias control of the 5ghz pa using a 6bit dac vdda33t k15 supply - usb2.0 transceiver supply dp k16 analog - usb2.0 data p signal gp1-8 k2 bidir down pe2 gndd k3 supply none digital io and core ground gp2-0 k4 bidir down serial flash clock (serclk) gp1-11 l1 bidir down antsel loop48 l13 analog none loop compensation network for 48mhz output pll vdda6 l14 analog none analog supply for pa bias dac gnda6 l15 analog none analog ground for pa bias nc l16 none none no connect, no pad gp1-5 l2 bidir down synthclk gp2-10 l3 bidir up serial flash chip select and rx/tx observe gp1-12 l4 bidir up trsw iovddd m1 supply none digital io supply (3.3v) gndapll m13 analog none pll ground vddapll m14 analog none pll supply voltage vddapll m15 analog none pll supply voltage pabias2g m16 analog none pabiassel5g = 0 for bias control of the 2.4ghz pa using a 6bit dac gp1-7 m2 bidir down pa_pe2g 2.4ghz pa enable. gp1-0 m3 bidir down pe1 gp1-9 m4 bidir down pll_ld (pll lock detect) corevddd n1 supply none digital core supply(1.8v) compiq n10 analog none compensation cpa for tx dacs rx_if_det n11 analog none overload detector input vdda5 n12 analog none analog supply for rx and tx agc dacs comptx n13 analog none compensation cap for tx agc dac vddapll n14 analog none pll supply voltage loop80 n15 analog none loop compensation network for 80mhz output pll table 1: GW3887A signal descriptions (sheet 3 of 5) pin name bga ball assignment pad type pin i/o type description
november 12, 2004 GW3887A data sheet do-406971-ds conexant systems, inc. issue 2 proprietary - use pursuant to nda 5 fsadpabias n16 analog none full scale adjust resistor for pa bias dac gp1-6 n2 bidir down synthdat lfxtalout n3 xtal output ------- low frequency (32khz) crystal pad lfxtalin n4 xtal input -------- low frequency (32khz) crystal pad gndd n5 supply none digital io and core ground gnda1 n6 analog none analog ground to 12bit dacs fsadoff n7 analog none full scale adjust resistor for 12bit dacs vdda3 n8 analog none analog supply to adcs gnda3 n9 analog none analog ground to adcs gndd p1 supply none digital io and core ground fsadiq p10 analog none full scale adjust resistor for tx dacs gnda4 p11 analog none analog ground for tx dacs rx_ifagc_n p12 analog none iout- for bb rx agc dac (bb_agc-) fsadtx p13 analog none full scale adjust resistor for tx agc dac vsub2 p14 analog none substrate pad (ground) loop44 p15 analog none loop compensation network for 44mhz output pll gndapll p16 analog none pll ground gp1-4 p2 bidir down synth_le gp1-10 p3 bidir down trsw vdda1 p4 analog none analog supply to offset dacs (2.85v) vddd0 p5 analog none offset dacs digital supply (2.85v) vdda2 p6 analog none analog supply to offset dacs vref p7 analog none band gap voltage reference input iref p8 analog none current reference resistor vdda4 p9 analog none analog supply to tx dacs iovddd r1 supply none digital io supply (3.3v) qout_p r10 analog none iout+ for q tx dac (txq+) tx_iq_det r11 analog none when calmodeen=1 this is selected as input to txdet adc comprx r12 analog none compensation cap for rx agc dac gnda5 r13 analog none analog ground for rx and tx agc dac vddd1 r14 analog none digital supply for dacs other than offset (2.85v) nc r15 none none no connect, no pad gndapll r16 analog none pll ground gp2-14 r2 bidir up led0 corevddd r3 supply none digital core supply(1.8v) vsub1 r4 analog none substrate tie (ground) nc r5 none none no connect, no pad compioff r6 analog none comp pin for offset dacs iin_n r7 analog none input signal for i rx adc (rxi-) qin_p r8 analog none input signal + for q rx adc (rxq+) iout_p r9 analog none iout+ for i tx dac (txi+) gp1-1 t1 bidir down hb_lb (high band/ low band) high band when qout_n t10 analog none iout- for q tx dac (txq-) pa_det t11 analog none when calmodeen=0 this is select as input to txdet adc rx_ifagc_p t12 analog none iout+ for bb rx agc dac (bb_agc+) fsadrx t13 analog none full scale adjust resistor for rx agc dac table 1: GW3887A signal descriptions (sheet 4 of 5) pin name bga ball assignment pad type pin i/o type description
GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 6 proprietary - use pursuant to nda issue 2 2 thermal information thermal resistance informatio n is provided in table 2. maximum storage temperature range . . . . . . . -65 c to 150 c maximum junction temperature . . . . . . . . . . . . 125 c note: for recommended soldering conditions refer to do-405727-tc technical brief (tb334) - guidelines for soldering surface mount components to pc boards. tx_ifagc t14 analog none iout for tx agc dac gndd1 t15 analog none digital ground for dacs other than offset nc t16 none none no connect, no pad gndd0 t2 analog none offset dacs digital ground qoout_p t3 analog none iout+ for q offset dac (qoffset+) qoout_n t4 analog none iout- for q offset dac (qoffset-) ioout_p t5 analog none iout+ for i offset dac (ioffset+) ioout_n t6 analog none iout- for i offset dac (ioffset-) iin_p t7 analog none input signal + for i rx adc (rxi+) qin_n t8 analog none input signal for q rx adc (rxq-) iout_n t9 analog none iout- for i tx dac (txi-) table 2: thermal resistance a a. ja is measured with the component mounted on high effective thermal conductivity test board in free air. refer to do-406099-tc technical brief(tb379) - thermal characterization of packaged semiconductor devices for details. product ja ( o c/w) bga package 42 table 1: GW3887A signal descriptions (sheet 5 of 5) pin name bga ball assignment pad type pin i/o type description
november 12, 2004 GW3887A data sheet do-406971-ds conexant systems, inc. issue 2 proprietary - use pursuant to nda 7 3 electrical specifications the GW3887A has an esd classification of class 1c. electrical specifications for the GW3887A are provided in table 3. warning: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the de vice at these or any othe r conditions above those indicated in the operational sections of this specification is not implied. table 3: electrical specifications a (sheet 1 of 2) parameter symbol test conditions min typ max units absolute maximum ratings supply voltage v cc -3.33.6v supply voltage v cc - 2.85 3.3 v supply voltage vdd_core - 1.8 1.98 v input, output or i/o voltage -gnd - 0.3v cc + 0.3 v operating conditions voltage vdd_i/o - 3.0 3.3 3.6 v voltage vddd - 2.7 2.85 3.3 v voltage vdda_pll - 2.7 2.85 3.3 v voltage vdda - 2.7 2.85 3.3 v voltage vdd_core - 1.62 1.8 1.98 v ambient temperature range - - -40 85 o c dc electrical specifications power supply current (3.3v) i ccop v cc = 3.6v, clk frequency 80mhz - - 10 ma power supply current 2.85v) i ccaop v = 3.3v, rx - - 100 ma power supply current (1.8v) i core v = 1.98v, rx 54mbps packet - - 300 ma standby current (3.3v) i ccstby vcc = 3.3v, using 32khz lf xtal, t a = 25c - - 300 a standby current (2.85v) i ccstby v = 2.85v, using 32khz lf xtal, t a = 25c - - 150 a standby (1.8v) i ccstby v = 1.8v, using 32khz lf xtal, t a = 25c - - 100 a input leakage current i i v cc = max, input = 0v or v cc -15 1 15 a output leakage current i o v cc = max, input = 0v or v cc -15 1 15 a logical one input voltage v ih v cc = max, min (v cc =vdd_i/o) 0.7v cc - - v logical zero input voltage v il v cc = min, max (v cc =vdd_i/o) - - 0.3v cc v logical one output voltage v oh i oh = -1ma, v cc = min (v cc =vdd_i/o) 0.9v cc -- v logical zero output voltage v ol i ol = 2ma, v cc = min (v cc =vdd_i/o) - 0.1 0.1v cc v input capacitance c in clk frequency 1mhz. all measurements referenced to gnd. t a = 25 c -510pf output capacitance c out clk frequency 1mhz. all measurements referenced to gnd. t a = 25 c -510pf schmitt hysteresis - 0.4 - 0.6 v
GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 8 proprietary - use pursuant to nda issue 2 ac electrical specifications clock signal timing osc clock frequency (40mhz 20ppm max, duty cycle 45/55) t cyc -40-mhz synthesizer synthclk(gp1-5) width hi t sclkhi 50 - - ns synthclk(gp1-5) width hi t sclklo 50 - - ns synthesizer data setup time (syndata, gp1-6) t synsetup 50 - - ns synthesizer data hold time t synhold 10 - - ns le pulse width (le_if, gp1-1 and le_rf gp1-2) t le 50 - - ns a. controlled via design or process parameters and not directly tested. table 3: electrical specifications a (sheet 2 of 2) parameter symbol test conditions min typ max units 4 mac overview the GW3887A mac uses an arm946e-s core. the mac is capable of operating at frequencies from 32khz in a reduced functionality power save mode up to 80mhz in normal operation. the GW3887A is equipped with on chip memory, which is used for instruction memory and data buffers. no external sram is required. the GW3887A is designed for use with a usb 2.0 host interface in accordance with the usb 2.0 specification. the GW3887A is designed for device side applications. the tmsel[3:0] signals are used to select special test modes and are unterminated for standard applications. the GW3887A is equipped with 31 general purpose i/os. these gpios are divided into two groups, gp1[15:0] and gp2[14:0]. in general, the gp1 i/os are used for radio control functions while the gp2 can be used for additional features under firmware control. 5 hardware wep engine the wired equivalent privacy module (wep) accelerates data encryption and decrypting providing a level of security for a wireless network that is intended to be at least as good as that of a wi red network. the encryption protocol used is rsa rc4. for more information about the wep rc4 encryption, see ieee std. 802.11 1994 section 8.2. 6 serial eeprom interface the GW3887A allows the usb vendor id and product id information and a small firmware image to be transferred from an off-chip serial non-volatile memory device to on-chip ram after a system reset. this allows a system vendor specific configuration. the operating frequency of the serial port is 400khz with a voltage of 3.3v. figure 2: small serial eeprom interface 7 reset power-on reset must be asse rted via the reset# pin to the GW3887A until 10 s after establishing acceptable power supply levels and stable clock signals. the tmsel[0.3] are sampled on th e rising edge of reset# to determine the boot mode. these pins have internal pull down resistors with an effective resistance of about 50k. 8 baseband processor interface the interface to the baseband processor is mostly internal, but some of the connections are visible on the gp2 and test ports when properly configured. GW3887A pull-up gp2-1 (sd) gp2-0 (scl) note: must operate at 400khz at 3.3v dc. 24c64 (note) a2 a1 ao sda scl wp
november 12, 2004 GW3887A data sheet do-406971-ds conexant systems, inc. issue 2 proprietary - use pursuant to nda 9 9 radio power sequencing the GW3887A provides a numb er of firmware controlled pins that ar e used for controlling the power sequencing components in the radio. packet transmission requires precise control of the radio. idea lly, energy at the antenna ceas es after the last symbol of information has been transmitted. since the GW3887A is designed for use with both 5ghz and 2.4ghz radios, it provides signals capable of controlling mu ltiple power amplifie rs or one dual band amplifier. additio nally, the transmit/ receive switch must be controlled properly to protect the receiver. it's also impo rtant to apply appropriate modulation to the pa while it's active. signaling sequences for the beginn ing and end of normal transmissions are illustrated in figure 3. figure 3: transmit control signal sequencing a transmission begins with a transmit enable (tx_enable ) to the baseband processor inside the GW3887A. this enable activates t he transmit state machine in t he bbp. next, 2gpabias acti vates the pa for 802.11b or g transmission followed by pe2 being activa ted. alternately 5gpabias can activate the pa for 802.11a transmission. lastly, the transmit/receive switch is configured for transmission via the differential pair tr_sw and tr_sw_bar. delays for these signals related to the initiation of transmission are referenced to tx_enable. after the GW3887A sends the last data, it de-asserts the appropriate pabias signal, pe2, and tr_sw. pe1 and pe2 encoding details are found in table 4. note that during normal receive and transmit operation that pe1 is static and pe2 toggles for receive and transmit states. table 4: power enable states a a. pll_pe is controlled via the serial interface, and can be used to disable the internal synthes izer, the actual synthesizer control is an and function of pll_pe, and a result of the or function of pe1 and pe2. pe1 and pe2 will directly control the power enable functionality of the lo buffer(s)/phase shifter. pe1 pe2 pll_pe power down state 0 0 1 receive state 1 1 1 transmit state 1 0 1 pll active state 0 1 1 pll disable state x x 0 pe1 pe2 tr_sw tr_sw_bar
GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 10 proprietary - use pursuant to nda issue 2 10 master clock and low-frequency crystal the GW3887A mac controller accepts the same clock signal as the phy baseband processor (40mhz), thereby avoiding the need for a separa te, mac-specific oscillator. the GW3887A also has a low- frequency oscillator. this low-frequency oscillator is in tended for use with a 32khz, tuning-fork type watch cr ystal to permit accurate timekeeping with very low power consumption during sleep state. a very low power sleep mode allows the GW3887A device to be clocked from an external crystal source, in place of the clk input. an output, oscenable, is deasserted to allow the external oscilla tor that generates clkin to be disabled to save power. when the clocks have switched, all internal clocks are generated from the crystal source. to transition out of deep sl eep, the oscenable output is asserted to re-enable the ex ternal oscillator. some time later (typically 10ms), the o scillator outputs are stable and the GW3887A device is switched back to the high frequency clk source. figure 4: 32khz crystal 11 power up sequencing i/o structures may draw excessive current if the core voltage is not applied which, when prolonged and excessive, can reduce the usable life of the device. the safest way to power up the device is to sequence the core and i/o power. the core should be powered up prior to the i/o block. the i/o voltage should be applied after the core voltage has reached at least 90% of its regulated level. bringing the core and i/o supplies to their respective regulation levels in a maximum time frame of 100ms moderates the stresses placed on both the power supply and the device. sequencing is not required when powering down. however, a ll power must be removed within 100ms of the removal of any power supply. from figure 5, the sequence delay for turning on the i/o power supply (t io -t pg ) should be no less than 0ms and no greater than 100ms. 12 proper handling all integrated circuits are susceptible to damage by inappropriate handling. damage is often caused by electrostatic discharge (esd) or inappropriate moisture content when soldering. the GW3887A has a moisture sensitivity classification of level 2 for GW3887Aik and GW3887Aik-t5 and level 3 for GW3887Aikz-t5 in accordance with ipc/jedec j-std-020a and should be handled accordingly. xtalin xtalout x1 c1 c2 10m ? 15pf 200pf 220k figure 5: power sequencing 1.62v 1.8 v t 0 t pg t io t 0 = initial turn on of core power supply t pg = time taken to reach 90% of intended core voltage t io = initial application of io power supply 3.3v i/o power core power
november 12, 2004 GW3887A data sheet do-406971-ds conexant systems, inc. issue 2 proprietary - use pursuant to nda 11 13 outline diagrams figure 6: plastic ball grid array packages (bga) notes for figure 6 and table 5: 1. controlling dimension: mi llimeter. converted inch dimensions are not necessarily exact. 2. dimensioning and tolerancing conform to asme y14.5m-1994. 3. ?md? and ?me? are the maximum ball matrix size for the ?d? and ?e? dimensions, respectively. 4. ?n? is the maximum number of balls for the specific array size. 5. primary datum c and seating plane are defined by the spherical crowns of the contact balls. 6. dimension ?a? includes standoff height ?a1?, package body thickness and lid or cap height ?a2?. 7. dimension ?b? is measured at the maximum ball diameter, parallel to the primary datum c. 8. pin ?a1? is marked on the top and bottom sides adjacent to a1. 9. ?s? is measured with respect to datum?s a and b and defines the position of the solder balls nearest to package centerlines. when there is an even number of balls in the outer row the value is ?s? = e/2. top view d a1 bottom view p n l m j k g h f e 8 13 14 12 11 10 9 corner 765 3 42 c d a b 1 side view c a a1 a2 bbb c aaa a1 e a b e1 d1 b s all rows and columns s m a b c c 0.15 0.08 m 0.006 0.003 a1 a1 corner i.d. e a a c r t 15 16 corner corner i.d. seating plane table 5: v192.14x14b 192 ball plastic ball grid array package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.010 0.014 0.25 0.35 - a2 0.026 0.035 0.67 0.90 - b 0.014 0.018 0.35 0.45 7 d/e 0.547 0.555 13.90 14.10 - d1/e1 0.468 0.476 11.90 12.10 - n 192 192 - e 0.032 bsc 0.80 bsc - md/me 16 x 16 16 x 16 3 bbb 0.004 0.10 - aaa 0.005 0.12 -
for additional information, contact conexant systems, inc. (together with its subsidiaries, ?conexant?) at 1-888-855-4562 (toll-free within the u.s. and canada) or 1-732-345-7500 , or visit the conexant internet site at www.conexant.com . important notice: conexant has taken all commercially reas onable effort to ensure that the information contained in this document is accurate, however we realize that errors do occur. conexant continually strives to improve the quality of its products and documentation and, as such, may make changes to this document at any time without notice. if you find errors, or inform ation that may be missing, please contac t your conexant sales representative. conexant advises all customers to ensure that t hey have the latest version of this data sheet and to verify, be fore placing orders, that information being relied on is current and complete. conexant does not, however, assume any responsibility for the use of the i nformation in this data sheet, nor for any infringements of patents or other rights of thir d parties which may result from its use. readers of this doc ument who are designers remain responsible for their own system designs and for ensuring that their overall system design satisfie s their design object ives, taking due account of the specifications of all equipment and software which may be incorporated into their design. please be reminded that diffe rences in system hardware and software design or configur ation may affect actual performance. no licenses to patents, copyrights, trade secrets or other intell ectual property of conexant or any of its subsidiaries are gra nted by this document. conexant assumes no liability whatsoever, and disclaims any express or im plied warranty relating to the sale or license of the products described in this document, including liability or warranties relating to fi tness for a particular purpose, merchantability, or infringement . this conexant proprietary document is intended only for use as specif ied in a non-disclosure agreement with t he company or one of its subsidiaries. this document is the property of conexant. no part of this doc ument may be copied, reproduced, stored in a retrieval system, t ranslated, or transmitted in any form, or by any means, nor may any part of th is document be used as the basis for manufacture or sale of any items or software without the express written consent of conexant. prism gt and worldradio are trademarks of conexant. third party brands, names, and marks are the property of their respective owners. copyright ? 2003, 2004 globespanvirata, inc., a who lly owned subsidiary of conexant systems, inc. all rights reserved GW3887A data sheet november 12, 2004 conexant systems, inc. do-406971-ds 12 proprietary - use pursuant to nda issue 2 14 order information table 6: ordering information part number package package drawing # temp. range (c) pack method minimum orderable quantities GW3887Aik 192 pin bga v192.14x14b -40 to 85 tray 90 GW3887Aik-tk 192 pin bga tape and reel 1000 GW3887Aikz-tk a a. lead free products employ special lead free material sets; mold ing compounds / die attach materials and 100% lead free termin ation fin- ishes, which are compatible with both snpb and lead free solder ing operations. lead free products are msl classified at lead fr ee peak reflow temperatures that meet or exceed the lead free requirements of ipc/jedec j std-020b. lead free192 pin bga tape and reel 1000

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